// (C) 2022 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other 
// software and tools, and its AMPP partner logic functions, and any output 
// files from any of the foregoing (including device programming or simulation 
// files), and any associated documentation or information are expressly subject 
// to the terms and conditions of the Intel Program License Subscription 
// Agreement, Intel FPGA IP License Agreement, or other applicable 
// license agreement, including, without limitation, that your use is for the 
// sole purpose of programming logic devices manufactured by Intel and sold by 
// Intel or its authorized distributors.  Please refer to the applicable 
// agreement for further details.

`ifndef LOGIC_SVH
`define LOGIC_SVH

`ifdef SYNTHESIS
    `ifdef OVL_ASSERT_ON
        `undef OVL_ASSERT_ON
    `endif
`elsif VERILATOR
    /* Define: SYNTHESIS
     *
     * Enable only synthesizable parts of HDL.
     */
    `define SYNTHESIS
`endif

`include "logic_modport.svh"

`ifdef OVL_ASSERT_ON
`define OVL_VERILOG
`define OVL_SVA_INTERFACE
`include "std_ovl_defines.h"
`endif

`endif /* LOGIC_SVH */
